FIG. 1 illustrates an exemplary application of a serial bus of the related art. The exemplary configuration of the computer system illustrated in FIG. 1 includes: a central processing unit (CPU) 10; a memory control unit (MCU) 11; memory 12; IO adapters 14 to 16 for communicating data with various peripheral control apparatus such as read-only memory (ROM) 17 and a local area network (LAN) 18; and an IO unit (IOU) 13 for controlling the IO adapters 14 to 16.
Data transmission among computers and among computer components has been conducted in the related art by means of transmission using a serial bus and transmission using a parallel bus. Since higher pin counts entail higher costs in semiconductor integrated circuits, a serial bus is often used for data transmission where speed is not critical, in order to reduce the pin count. For this reason, a serial bus has been used between the ROM 17 and the IO adapter 15, between the LAN 18 and the IO adapter 16, as well as between the IO adapters 14 to 16 and the IOU 13 in FIG. 1, for example.
FIG. 2 illustrates an exemplary application of a high-speed serial bus. As illustrated in FIG. 1, serial transmission is often used in the related art for connections with IO devices accessed at comparatively low speeds and similar situations which do not significantly affect the access latency from the CPU 10. However, as computer systems have increased in speed and other performance factors, components which do affect the access latency of the CPU have come to be used, such as the system bus 19-1 connecting the CPU 10 and MCU 11, as well as the system bus 19-2 connecting the MCU 11 and IOU 13, as illustrated in FIG. 2. Serial buses have come to be used for such system buses because the use of serial transmission has an advantage in being immune to bit skew due to differences in wiring lengths, which poses a problem for parallel transmission.
In interfaces that transmit data using a serial bus, the transmitter circuit connected to the serial bus transmits by first converting parallel data into serial data. The receiver circuit connected to the serial bus receives the data transmitted as serial data by restoring the data to parallel data. When transmitting data using such a serial bus, it is desired for reference positions in the parallel data to be matched at the transmitter and the receiver. In high-speed serial transmission, for example, a training period is typically provided during the initial stages of operation or at another specific time. During the training period, specific codes are transmitted, and preparations are made for data communication. Thus, the process to match the reference positions in the parallel data at the transmitter and the receiver is also conducted during such a training period.
In the case of high-speed serial transmission, such as when converting and transmitting 8-bit parallel data as serial data, for example, an 8B10B encoder circuit may be used in some cases to convert the 8-bit data into 10-bit data before transmission. With the 8B10B encoding scheme, the data and clock are transmitting on the same line by embedding clock signal information into the serial data.
With the 8B10B encoding scheme, the numbers of “0” and “1” bits in the data transmitted during serial communication are equalized, thereby maintaining a direct current (DC) balance and making it possible to detect data corruption on the transmission line to some degree. In addition, by converting 8-bit data into 10-bit data, it becomes possible to transmit special codes that carry special meanings different from the transmitted data. Such special codes may be endowed with special meanings and used for control or other functions during data transmission. Furthermore, such special codes are utilized to match data boundaries at the transmitter and the receiver.
Japanese Patent No. 3094973 discloses technology configured to target specific comma signals included in serial data encoded with 8B10B, and synchronize words in incoming data by detecting whether or not comma signals are included in input serial data. Meanwhile, Japanese Unexamined Patent Application Publication No. 2009-94891 discloses technology configured to detect specific codes included in serial data by means of a pattern detector made up of two ring buffers, and determine times for acquiring the serial data as parallel data.
However, in the related art, high-speed data transmission of 10 gigabits per second (Gbps) or greater is problematic because of insufficient operating speed in the circuit for detecting the boundaries of the transmission data. In addition, when serial communication is used in a system bus or similar component, it is also desired to minimize access latency. Consequently, it is desirable to realize high-speed serial transmission while reducing access latency.
Related arts are disclosed in Japanese Patent No. 3094973 and Japanese Laid-open Patent Publication No. 2009-94891.